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? semiconductor components industries, llc, 2013 february, 2013 ? rev. 9 1 publication order number: NOIL1SM4000A/d NOIL1SM4000A lupa4000: 4 megapixel high speed cmos sensor features ? 2048 x 2048 active pixels ? 12 m x 12 m square pixels ? 24.6 mm x 24.6 mm optical format ? monochrome or color digital output ? 15 frames per second (fps) at full resolution ? pipelined global shutter ? random programmable region of interest (roi) readout and subsampling modes ? serial peripheral interface (spi) ? operational range: 0 c to 60 c ? 127-pin pga package ? 220 mw power dissipation ? these devices are pb ? free and are rohs compliant applications ? intelligent traffic system ? high speed machine vision overview the lupa4000 is a cmos image sensor (cis) with a 4.0 megapixel resolution 2048 x 2048 pixel format. this document describes the interfacing and driving of the lupa4000 image sensor. this 4 megapixel cmos active pixel sensor features synchronous shutter and a maximal frame rate of 15 fps in full resolution. the readout speed can be boosted by sub-sampling and windowed roi readout. high dynamic range scenes can be captured using the double and multiple slope functionality. the sensor uses a 3-wire spi and is housed in a 127-pin ceramic pga package. the lupa4000 is available in mono and color option. ordering information marketing part number description package NOIL1SM4000A-gdc mono with glass 127 ? pin pga noil1sc4000a-gdc color with glass note: refer to ordering code definition on page 26 for more information. http://onsemi.com figure 1. lupa4000 photo
NOIL1SM4000A http://onsemi.com 2 contents features 1 ..................................... applications 1 ................................. overview 1 .................................... ordering information 1 ......................... specifications 3 ................................ key specifications 3 .......................... absolute maximum ratings 3 ................... electrical specifications 4 ...................... overview 5 .................................... color filter array 5 ........................... sensor architecture 6 ........................... image core 6 ................................ output amplifier 6 ............................ pixel array drivers 7 .......................... column amplifiers 7 .......................... analog-to-digital converter 7 ................... operating modes 8 ............................. global shutter mode 8 ......................... non destructive readout (ndr) 9 ............... operation and signalling 9 ...................... power supplies and ground 9 ................... biasing and analog signals 10 ................... pixel array signals 10 .......................... digital signals 11 .............................. test signals 12 ................................ frame rate and windowing 12 ................... timing and readout of image sensor 13 ............ timing of pixel array 13 ........................ readout of image sensor 14 ..................... serial peripheral interface 19 ..................... pin list 20 ..................................... package drawing 24 ........................... mechanical package specification 25 .............. glass lid 26 .................................. handling precautions 26 ......................... limited warranty 26 ............................ return material authorization (rma) 26 ........... acceptance criteria specification 26 ............... ordering code definition 26 ...................... acronyms 27 ................................... glossary 28 .................................... appendix a: frequently asked questions 30 ........
NOIL1SM4000A http://onsemi.com 3 specifications key specifications general specifications parameter specifications active pixels 2048 x 2048 pixel size 12 m x 12 m optical format 24.6 mm x 24.6 mm pixel type global shutter pixel architecture shutter type pipelined global shutter master clock 33 mhz windowing (roi) randomly programmable roi readout windowed and subsampled readout possible power dissipation 200 mw package type 127 pga electro ? optical specifications parameter typical specifications frame rate 15 fps at full resolution conversion gain 11.5 v/e - responsivity at 550 nm 1550 (v/s)/(w/m 2 ) fill factor (ff) 37.5% parasitic light sensitivity < 1/7600 at 550 nm full well charge 95700 e - quantum efficiency (qe) 36% (qe x ff) fixed pattern noise (fpn) 16 mv photo response nonuniformity (prnu) 3% of signal dynamic range 66 db (single slope), 90 db (multiple slope) dark signal 22 mv/s at +20 c with 50 ms integration time dark signal doubling temperature 8.65 c absolute maximum ratings absolute maximum ratings (note 1) ????????? ????????? symbol ??????????????? ??????????????? ???? ???? ????? ????? ???? ???? ????????? ????????? abs (2.5 v supply group) ??????????????? ??????????????? ???? ???? ? 0.5 ????? ????? ???? ???? ????????? ????????? ??????????????? ??????????????? ???? ???? ? 0.5 ????? ????? ???? ???? ????????? ????????? ????????? ??????????????? ??????????????? ??????????? ??????????? ??????????? ??????????????? ??????????????? ????????? ????????? ? up ??????????????? ??????????????? ? up rating ??????????? ??????????? ????????? ????????? ????????? ??????????????? ??????????????? ???? ???? ? 40 ????? ????? ???? ???? c ??????????????? ??????????????? c ???? ???? ????? ????? ???? ???? recommended operating ratings ????????? ????????? t j (note 2) ??????????????? ??????????????? ???? ???? ????? ????? ???? ???? c 1. absolute maximum ratings are limits beyond which damage may occur. exceeding the maximum ratings may impair the useful life o f the device. 2. operating ratings are conditions at which operation of the device is intended to be functional. 3. on semiconductor recommends that customers become familiar with, and follow the procedures in, jedec standard jesd625 ? a. refer to application note an52561. 4. the lupa4000 complies with jesd22 ? a114 hbm class 0 and jesd22 ? c101 class i. it is recommended that extreme care be taken while handling these devices to avoid damages due to esd event. 5. the lupa4000 does not have latch ? up protection.
NOIL1SM4000A http://onsemi.com 4 electrical specifications power supply ratings limits in bold apply for t j = t min to t max , all other limits t j = +30 c (notes 1 and 3) parameter description min typ max [2] units power supply parameters vdd core digital supply ? 10% 2.5 +10% v idd core digital current ? 1 200 ma vaa analog supply voltage ?10% 2.5 +10% v iaa analog supply current ? 7 50 ma vpix pixel supply voltage ?5% 2.6 +5% v ipix pixel supply current ? 12 500 ma voo output stage power supply ?10% 2.5 +10% v ioo output stage current ? 20 ? ma va3 column readout module supply ?1% 3.3 +1% v ia3 column readout module current ? 10 50 ma vmem_l power supply memory element (low level) ?5% 2.6 +5% v imem_l power supply memory element current (low level) ? 1 200 ma vmem_h power supply memory element (high level) ?5% 3.3 +5% v imem_h power supply memory element current (high level) ? 1 200 ma vres power supply to reset drivers ? 5% 3.5 +5% v ires power supply current to reset drivers ? 1 200 ma vres_ds power supply to multiple slope drivers ?5% 2.5 +5% v ires_ds power supply current to multiple slope drivers ? 1 200 ma vpre_l power supply for pre-charge off-state ?0.4 0 0 v vddd digital supply to adc drivers ?10% 2.5 +10% v iddd digital supply current to adc drivers ? 1 200 ma vdda analog supply to adc drivers ?5% 2.5 +5% v idda analog supply current to adc drivers ? 1 200 ma pd total power consumption ? 200 ? mw sensor requirements fps frame rate at full resolution (global shutter) ? ? 15 fps fps_roi1 xres x yres = 1024 x 2048 ? ? 31 fps fps_roi2 xres x yres = 1024 x 1024 ? ? 62 fps fps_roi3 xres x yres = 640 x 480 ? ? 210 fps fot frame overhead time ? 5 ? s rot row overhead time (can be further reduced) ? 200 ? ns 1. all parameters are characterized for dc conditions after thermal equilibrium is established. 2. the maximum currents are peak currents which occur once per frame. 3. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high ? impedance circuit.
NOIL1SM4000A http://onsemi.com 5 overview the lupa4000 cmos active pixel sensor features a global shutter with a maximum frame rate of 15 fps in full resolution. the readout speed is boosted by sub sampling and the windowed roi readout. high dynamic range scenes can be captured using the multiple slope functionality. subsampling reduces resolution while maintaining the constant field of view and an increased frame rate. the sensor uses a 3-wire spi. it requires only one master clock for operation up to 15 fps. the sensor is available in a monochrome version or bayer (rgb) patterned color filter array. it is placed in a 127-pin ceramic pga package. color filter array the color version of lupa4000 is available in bayer (rgb) patterned color filter array. the orientation of rgb is shown in figure 2. figure 2. color filter array lupa4000 pixel array x_readout direction y_readout direction g (0.1) b (1.1) r (0.0) g (1.0) the spectral response for the mono and color device is shown in figure 3. figure 3. spectral response curve for mono and color
NOIL1SM4000A http://onsemi.com 6 sensor architecture the lupa4000 architecture is shown in figure 4. image core the image core consists of a pixel array , one x-addressing and two y -addressing registers (only one drawn), pixel array drivers, and column amplifiers. the active pixel area is read out in progressive scan by one or two output amplifiers. the output amplifiers operate at a nomimal speed of 66-mhz pixel rate, or 33-mhz pixel rate if two output amplifiers are used to read out the imager. the image sensor is designed for operation up to 66 mhz. the structure allows having a programmable addressing in the x-direction and y-direction in steps of two. only even start addresses in x-direction and y-direction are possible. the starting point of the address can be uploaded using the spi. figure 4. block diagram of image sensor x-shift registers dac 2 differential outputs select drivers column amplifiers spi clk_x?sync_x eos_x y-shift registers clk_y? sync_y eos_y pixel (0,0) logic blocks on-chip drivers (reset, mem_hl, precharge, sample) pixel array (2048 x 2048) output amplifier the sensor has two output amplifiers. a single amplifier can be operated at 66 mpixels/sec to bring the whole pixel array of 2048 by 2048 p ixels at the required frame rate. the second output amplifier can be enabled in parallel if the clock frequency is decreased to 33 msamples/sec. using only one output-stage, the output signal is the result of multiplexing between the two internal buses. when using two output-stages, both outputs are in phase. each output-stage has two outputs. one output is the pixel signal; the second output is a dc signal, which offset can be programmed using a 7-bit word. the dc signal is used for common mode rejection between the two signals. the disadvantage is an increase in power dissipation. however, this can be reduced by setting the highest dac voltage using the spi. figure 5. output stage architecture image sensor spi dac 7 bits output 1 (pixel signal) output 2 (dc signal) the output voltage of output 1 is between 1.3 v (dark level) and 0.3 v (white level) and depends on process variations and voltage supply settings. the output voltage of output2 is determined by the dac.
NOIL1SM4000A http://onsemi.com 7 pixel array drivers the image sensor has on-chip drivers for the pixel array signals the driving on system level is easy and flexible; the maximum currents applied to the sensor are also controlled on-chip. this means that the charging on sensor level is fixed; the sensor cannot be overdriven externally. the operation of the on-chip drivers is explained in timing and readout of image sensor on page 13. column amplifiers the column amplifiers are designed for minimum power dissipation and minimum loss of signal, resulting in multiple biasing signals. the column amplifiers have an integrated ?voltage-averaging? feature. in the voltage-averaging mode, the voltage average between two columns is read out. in this mode, only 2:1 pixels must be read out. to achieve the voltage-averaging mode, an additional external digital signal called voltage-averaging is required in combination with a bit from the spi. analog-to-digital converter the lupa4000 has two 10-bit flash adcs running nominally at 10 msamples/s. the adc block is electrically separated from the image sensor. the inputs of the adc must be tied externally to the outputs of the output amplifiers. if the internal adc is not used, then the power supply pins to the adc and the i/os must be grounded. even in this configuration, the internal adcs are not able to sustain the 66 mpixel/sec provided by the output amplifier when run at full speed. one adc samples the even columns and the second adc samples the odd columns. although the input range of the adc is between 1 v and 2 v and the output range of the analog signal is between 0.3 v and 1.3 v, the analog output and digital input may be tied to each other directly. this is possible because there is an on-chip level-shifter located in front of the adc to lift up the analog signal to the adc range. errata for internal adcs use external adcs due to the limitation of the internal adc clock, not operational at system clock. no fix is intended to resolve this limitation. table 1. adc specifications parameter specification input range 1 v to 2 v (note 1) quantization 10 bits normal data rate 10 msamples/s differential nonlinearity (dnl) - linear conversion mode typ. < 0.4 lsb rms integral nonlinearity (inl) - linear conversion mode typ. < 3.5 lsb input capacitance < 2 pf power dissipation at 33 mhz 50 mw conversion law linear/gamma ? corrected 1. the internal adc range is typically 50 mw lower than the external applied adc_vhigh and adc_vlow voltages due to voltage drops over parasitic internal resistors in the adc. adc timing the adc converts the pixel data on the falling edge of the adc_clock, but it takes two clock cycles before this pixel data is at the output of the adc. this pipeline delay is shown in figure 6. figure 6. adc timing
NOIL1SM4000A http://onsemi.com 8 setting adc reference voltages figure 7. internal and external adc connections 2.5 v gnd_33 rhigh_adc rlow_adc radc vref_high ~2 v vref_low ~1 v the internal resistor r adc has a value of approximately 300 . the value of this resistor is not tested at sort or at final test. some modification may be required as the recommended resistors in figure 7 are determined by trade ? off between speed and power consumption. resistor typical value ( ) r adc_vhigh 75 r adc 300 r adc_vlow 220 operating modes the lupa4000 sensor operates in the global shutter mode. global shutter mode in the global shutter mode, light integration takes place on all pixels in parallel, although subsequent readout is sequential. figure 8 shows the integration and readout sequence for the synchronous shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously; after the integration time, all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and readout can occur in parallel or sequentially. figure 8. global shutter operation line number pipelined global shutter in pipelined global shutter mode, the integration and readout are done in parallel. images are continuously read and integration of frame n is ongoing during readout of the previous frame n-1. the readout of every frame starts with an fot, during which the analog value on the pixel diode is transferred to the pixel memory element. after the fot, the sensor is read out line by line and the readout of each line is preceded by the rot. figure 9 shows the exposure and readout timeline in pipelined global shutter mode.
NOIL1SM4000A http://onsemi.com 9 figure 9. integration and readout for pipelined shutter reset n exposure time n reset n+1 exposure time n+1 readout frame n-1 fot fot readout frame n non destructive readout (ndr) the sensor can also be read out in a non destructive way. after a pixel is initially reset, it can be read multiple times without resetting. the initial reset level and all intermediate signals can be recorded. high light levels saturate the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, use the latest samples. figure 10. principle of ndr time an active pixel array is read multiple times and reset only once. the external system intelligence takes care of the interpretation of the data. table 2 summarizes the advantages and disadvantages of non-destructive readout. table 2. advantages & disadvantages of ndr advantages disadvantages low noise, because it is true correlated double sampling (cds). system memory required to record the reset level and the intermediate samples. high sensitivity, because the conversion capacitance is kept low. requires multiples readings of each pixel, thus higher data throughput. high dynamic range, because the results includes signal for short and long integrations times. requires system level digital calculations. operation and signalling the signals are classified into the following groups: ? power supplies and grounds ? biasing and analog signals ? pixel array signals ? digital signals ? test signals power supplies and ground every module on chip including column amplifiers, output stages, digital modules, and drivers has its own power supply and ground. off chip, the grounds can be combined, but not all power supplies may be combined. this results in several different power supplies, but this is required to reduce electrical cross-talk and improve shielding, dynamic range, and output swing. on chip, the ground lines of every module are kept separately to improve shielding and electrical cross talk between them. an overview of the supplies is given in electrical specifications on page 4. the maximum currents mentioned in the specifications table are peak currents which occur once per frame (except for v res_ds in multiple slope mode). all power supplies should be able to deliver these currents except for vmem_l and vpre_l, which must be able to sink this current. the maximum peak current for vpix should not be higher than 500 ma. note that no power supply filtering on chip is implemented and noise on these power supplies can contribute immediately to the noise on the signal. the voltage supplies vpix and vaa must be noise free. startup sequence the lupa4000 goes in latch-up (draw high current) when all power supplies are turned on simultaneously. the sensor comes out of latch-up and starts working normally as soon as it is clocked. a power supply current limit of 400 ma is recommended to avoid damage to the sensor. avoid the time that the device is in the latch-up state, so clocking of the sensor should start as soon as the system is turned on. to avoid latch-up of the sensor, follow this sequence: 1. apply vdd 2. apply clocks and digital pulses to the sensor to count 1024 clock_x and 2048 clock_y pulses to empty the shift registers 3. apply other supplies
NOIL1SM4000A http://onsemi.com 10 biasing and analog signals the expected analog output levels are between 0.3 v for a white, saturated, pixel and 1.3 v for a black pixel. there are two output stages, each consisting of two output amplifiers, resulting in four outputs. one output amplifier is used for the analog signal resulting from the pixels. the second amplifier is used for a dc reference signal. the dc level from the buffer is defined by a dac, which is controlled by a 7-bit word downloaded in the spi. additionally, an extra bit in the spi defines if one or two output stages are used. table 3 summarizes the biasing signals required to drive this image sensor. to optimize biasing of column amplifiers to power dissipation, several biasing resistors are required. this optimisation results in an increase of signal swing and dynamic range. table 3. overview of bias signals signal comment related module dc level out_load connect with 60 k to voo and capacitor of 100 nf to gnd output stage 0.7 v dec_x_load connect with 2 m to vdd and capacitor of 100 nf to gnd x-addressing 0.4 v muxbus_load connect with 25 k to vaa and capacitor of 100 nf to gnd multiplex bus 0.8 v nsf_load connect with 5 k to vaa and capacitor of 100 nf to gnd column amplifiers 1.2 v uni_load_fast connect with 10 k to vaa and capacitor of 100 nf to gnd column amplifiers 1.2 v uni_load connect with 1 m to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v pre_load connect with 3 k to vaa and capacitor of 100 nf to gnd column amplifiers 1.4 v col_load connect with 1 m to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v dec_y_load connect with 2 m to vdd and capacitor of 100 nf to gnd y-addressing 0.4 v psf_load connect with 1 m to vaa and capacitor of 100 nf to gnd column amplifiers 0.5 v precharge_bias connect with 1 k to vdd and capacitor of at least 200 nf to gnd pixel drivers 1.4 v each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation. some modules have two biasing resistors: one to achieve the high speed and another to minimize power dissipation. pixel array signals the pixel array of the image sensor requires digital control signals and several different power supplies. this section explains the relation between the control signals and the applied supplies, and the internal generated pixel array signals. figure 11 illustrates the internal generated pixel array signals: reset, sample, precharge, vmem, and row_select. these are internal generated signals derived by on-chip drivers from external applied signals. row_select is generated by the y-addressing and is not discussed in this section reset: resets the pixel and initiates the integration time. if reset is high, then the photodiode is forced to a certain voltage. this depends on vpix (pixel supply) and the high level of reset signal. the higher these signals or supplies, the higher the voltage-swing. the limitation on the high level of reset and vpix is 3.3 v. it does not help to increase vpix without increasing the reset level. the opposite is true. additionally, it is the reset pulse that also controls the dual or multiple slope feature inside the pixel. by giving a reset pulse during integration, but not at full reset level, the photodiode is reset to a new value, only if this value is decreased due to light illumination. the low level of reset is 0 v, but the high level is 2.5 v or higher (3.3 v) for the normal reset and a lower (<2.5 v) level for the multiple slope reset. precharge: precharge serves as a load for the first source follower in the pixel and is activated to overwrite the current information on the storage node by the new information on the photodiode. precharge is controlled by an external digital signal between 0 v and 2.5 v. sample: samples the photodiode information onto the memory element. this signal is also a standard digital level between 0 v and 2.5 v. vmem: this signal increases the information on the memory element with a certain offset. this increases the output voltage variation. vmem changes between vmem_l (2.5 v) and vmem_h (3.3 v).
NOIL1SM4000A http://onsemi.com 11 figure 11. internal timing of pixel in figure 11, levels are defined by the pixel array voltage supplies; for correct polarities of the signals see table 4. the signals in figure 11 are generated from the on-chip drivers. these on-chip drivers need two types of signals to generate the exact type of signal. it needs digital control signals between 0 v and 3.3 v (internally converted to 2.5 v) with normal driving capability and power supplies. the control signals are required to indicate when they must occur and the power supplies indicate the level. vmem is made of a control signal mem_hl and 2 supplies vmem_h and vmem_l. if the signal mem_hl is the logic ?0? than the internal signal vmem is low, if mem_hl is logic ?1? the internal signal vmem is high. reset is made with two control signals, reset and reset_ds, and two supplies, vres and vres_ds. depending on the signal that becomes active, the corresponding supply level is applied to the pixel. table 4 summarizes the relation between the internal and external pixel array signals. table 4. overview of internal and external pixel array signals internal signal vlow vhigh external control signal low dc level high dc level precharge 0 0.45 v precharge (al) vpre_l controlled by bias-resistor sample 0 2.5 v sample (al) gnd vdd reset 0 2.5 v to 3.3 v reset (ah) and reset_ds (ah) gnd vres and vres_ds vmem 2.0 v to 2.5 v 2.5 v to 3.3 v mem_hl (al) vmem_l vmem_h for dual slope operation, give a second reset pulse to a lower reset level during integration. this is done by the control signal reset_ds and by the power supply vres_ds that defines the level to which the pixel must be reset. note that reset is dominant over reset_ds, which means that the high voltage level is applied for reset, if both pulses occur at the same time. multiple slopes are possible having multiple reset_ds pulses with a lower v res_ds level for each pulse given within the same integration time. the rise and fall times of the internal generated signals are not very fast (200 ns). in fact they are made rather slow to limit the maximum current through the power supply lines (vmem_h, vmem_l, vres, vres_ds, vdd). current limitation of those power supplies is not required. however, limit the currents to not higher than 400 ma. the power supply vmem_l must be able to sink this current because it must be able to discharge the internal capacitance from the level vmem_h to the level vmem_l. the external control signals should be capable of driving input capacitance of about 10 pf. digital signals the digital signals control the readout of the image sensor. these signals are: ? sync_y (ah [10] ): starts the readout of the frame. this pulse synchronises the y-address register: active high. this signal is also the end of the frame or window and determines the window width. ? clock_y (ah [10] ): clock of the y-register. on the rising edge of this clock, the next line is selected. ? sync_x (ah [10] ): starts the readout of the selected line at the address defined by the x-address register. this pulse synchronises the x-address register: active high. this signal is also the end of the line and determines the window length. ? clock_x (ah [10] ): determines the pixel rate. a clock of 33 mhz is required to achieve a pixel rate of 66 mhz. ? spi_data (ah [10] ): data for the spi. ? spi_clock (ah [10] ): clock of the spi. this clock downloads the data into the spi register.
NOIL1SM4000A http://onsemi.com 12 ? spi_load (ah [10] ): when the spi register is uploaded, then the data is internally available on the rising edge of spi_load. ? sh_kol (al [11] ): control signal of the column readout. it is used in sample and hold mode and binning mode. ? norowsel (ah [10] ): control signal of the column readout (see timing and readout of image sensor). ? pre_col (al [11] ): control signal of the column readout to reduce row blanking time. ? voltage averaging (ah [10] ): signal required obtaining voltage averaging of two pixels. notes: 10. ah: active high 11. al: active low test signals the test structures implemented in this image sensor are: ? array of pixels (6 x 12) that outputs are tied together: used for spectral response measurement. ? temperature diode (2): apply a forward current of 10 a to 100 a and measure the voltage v t of the diode. v t varies linear with the temperature (v t decreases with approximately 1.6 mv/ c). ? end of scan pulses (do not use to trigger other signals): ? eos_x: end of scan signal: is an output signal, indicating when the end of line is reached. it is not generated when windowing. ? eos_y: end of scan signal: is an output signal, indicating when the end of frame is reached. it is not generated when windowing. ? eos_spi: output signal of the spi to check if the data is transferred correctly through the spi. frame rate and windowing frame rate to acquire a frame rate of 15 frames/sec, the output amplifier should run at 66 mhz pixel rate or two output amplifiers should run at 33 mhz each, assuming an rot of 200 ns. the frame period of the lupa4000 sensor is calculated as follows: frame period = fot + (nr. lines x (rot + pixel period x nr. pixels) with: fot = 5 s nr. lines: number of lines read out each frame (y) nr. pixels: number of pixels read out each line (x) rot = 200 ns (nominal; can be further reduced) pixel period: 1/66 mhz = 15.15 ns example read out of the full resolution at nominal speed (66 mhz pixel rate): frame period = 5 s + (2048 x (200 ns + 15.15 ns x 2048) = 64 ms 15 fps. roi readout (windowing) windowing is achieved by an spi in which the starting point of the x-address and y-address is uploaded. this downloaded starting point initiates the shift register in the x-direction and y-direction triggered by the sync_x and sync_y pulse. the minimum step size for the x-address and the y-address is 2 (only even start addresses can be chosen). the size of both address registers is 10-bits. for instance, when the addresses 0000000001 and 0000000001 are uploaded, the readout starts at line 2 and column 2. table 5. frame rate as function of roi read out and sub sampling image resolution (x*y) frame rate [frames f/s] frame readout time [ms] comment 2048 x 2048 15 67 full resolution. 1024 x 2048 31 32 subsample in x-direction. 1024 x 1024 62 16 roi read out. 640 x 480 210 4.7 roi read out.
NOIL1SM4000A http://onsemi.com 13 timing and readout of image sensor the timing of the lup a4000 sensor consists of two parts. the first part is related to the control of the pixels, the integration time, and the signal level. the second part is related to the readout of the image sensor. as full synchronous shutter is possible with this image sensor, integration time and readout can be in parallel or sequential. in the parallel mode, the integration time of the frame i is ongoing during readout of frame i-1. figure 12 shows this parallel timing structure. the control of the frame?s readout and integration time are independent of each other with the only exception that the end of the integration time from frame i+1 is the beginning of the readout of frame i+1. figure 12. integration and readout in parallel read frame i read frame i+1 integration i+1 integration i+2 the lupa4000 sensor is also used in sequential mode (triggered snapshot mode) where readout and integration is sequential. figure 13 shows this sequential timing. figure 13. integration and readout in sequence integration frame i read frame i integration i+1 read frame i+1 timing of pixel array the first part of the timing is related to the timing of the pixel array. this implies control of integration time, synchronous shutter operation, and sampling of the pixel information onto the memory element inside each pixel. the signals required for this control are described in pixel array signals and in figure 11. figure 14 shows the external applied signals required to control the pixel array. at the end of the integration time from frame i+1, the signals mem_hl, precharge, and sample must be given. the reset signal controls the integration time, which is defined as the time between the falling edge of reset and the rising edge of sample. figure 14. pixel array timing the integration time is determined by the falling edge of the reset pulse. the longer the pulse is high, the shorter the integration time. at the end of the integration time, the information must be stored onto the memory element for readout.
NOIL1SM4000A http://onsemi.com 14 timing specifications for each signal are shown in table 6. ? falling edge of precharge is equal or later than falling edge of vmem. ? sample is overlapping with precharge. ? rising edge of vmem is more than 200 ns after rising edge of sample. ? rising edge of reset is equal or later than rising edge of vmem. table 6. timing specifications symbol name value a mem_hl 5 ? 8.2 s b precharge 3 ? 6 s c sample 5 ? 8 s d precharge ? sample > 2 s e integration time > 1 s the timing of the pixel array is straightforward. before the frame is read, the information on the photodiode must be stored onto the memory element inside the pixels. this is done with the signals mem_hl, precharge, and sample. when precharge is activated, it serves as a load for the first source follower in the pixel. sample stores the photodiode information onto the memory element. mem_hl pumps up this value to reduce the loss of signal in the pixel and this signal must be the envelop of precharge and sample. after mem_hl is high again, the readout of the pixel array starts. the frame blanking time or frame overhead time is thus the time that mem_hl is low, which is about 5 s. after the readout starts, the photodiodes can all be initialised by reset for the next integration time. the minimal integration time is the minimal time between the falling edge of reset and the rising edge of sample. keeping the slow fall times of the corresponding internal generated signals in mind, the minimal integration time is about 2 s. an additional reset pulse of minimum 2 s can be given during integration by asserting reset_ds to implement the double slope integration mode. readout of image sensor when the pixel information is stored in the memory element of each pixel, it can be read out sequentially. integration and readout can also be done in parallel. the readout timing is straightforward and is controlled by sync and clock pulses. figure 15 shows the top level concept of this timing. the readout of a frame consists of the frame overhead time, the selection of the lines sequentially, and the readout of the pixels of the selected line. figure 15. readout of image sensor (l: line selection, c: column selection) l2048 fot _ _ _ c2048 rot _ _ _ integration i+2 readout frame i readout lines readout pixels the readout of an image consists of the fot and the sequential selection of all pixels. the fot is the overhead time between two frames to transfer the information on the photodiode to the memory elements. figure 14 shows that at this time mem_hl is low (typically 5 ms). after the fot, the information is stored into the memory elements and a sequential selection of rows and columns makes sure the frame is read.
NOIL1SM4000A http://onsemi.com 15 x and y addressing to read out a frame, the lines are selected sequentially. figure 16 gives the timing to select the lines sequentially. this is done with a clock_y and sync_y signal. the sync_y signals synchronizes the y-addressing and initializes the y-address selection registers. the start address is the address downloaded in the spi multiplied by two. on the rising edge of clock_y the next line is selected. the sync_y signal is dominant and from the moment it occurs, the y-address registers are initialized. if a sync_y pulse is given before the end of the frame is reached, only a part of the frame is read. to obtain a correct initialization, sync_y must contain at least one rising edge of clock_y when it is active. figure 16. x and y addressing table 7. readout timing specifications symbol name value a sync_y > 20 ns b sync_y ? clock_y > 0 ns c clock_y ? sync_y > 0 ns d norowsel > 50 ns e pre_col > 50 ns f sh_col 200 ns g voltage averaging > 20 ns h sync_x ? clock_x > 0 ns as soon as a new line is selected, it must be read out by the output amplifiers. before the pixels of the selected line can be multiplexed onto the output amplifiers, wait for a certain time, indicated as the rot shown in figure 16. this is the time to get the data stable from the pixels to the output bus before the output stages. this rot is in fact lost time and rather critical in a high-speed sensor. different timings to reduce this rot are explained later in this section. during the selection of one line, 2048 pixels are selected. these 2048 pixels must be read out by one (or two) output amplifier. the pixel rate is the double frequency of the clock_x frequency. to obtain a pixel rate of 66 mhz, apply a pixel clock clock_x of 33mhz. when only one analog output is used, two pixels are output every clock_x period. when clock_x is high, the first pixel is selected; when clock_x is low, the next pixel is selected. consequently, during one complete period of clock_x two pixels are read out by the output amplifier. if two analog outputs are used each clock-x period one pixel is presented at each output.
NOIL1SM4000A http://onsemi.com 16 figure 17. x ? addressing the figure shows clock_x, sync_x, internal selection pixel 1 and 2, internal selection pixel 3 and 4, internal selection pixel 5 and 6. the first pixel selected is the x-address downloaded in the spi. the starting address is the number downloaded into the spi, multiplied by 2. windowing is achieved by a starting address downloaded in the spi and the size of the window. in the x-direction, the size is determined by the moment a new clock_y is given. in the y-direction, the sync_y pulse determines the size. the best way to obtain a window is by using an internal counter in the controller. figure 17 is the simulation result after extraction of the layout module from a dif ferent sensor to show the principle. in this figure, the pixel clock has a frequency of 50 mhz, which results in a pixel rate of 100 msamples/sec. figure 18 on page 17 shows the relation between the applied clock_x and the output signal.
NOIL1SM4000A http://onsemi.com 17 figure 18. output signal related to clock_x signal output 1 sync_x p clock_x: 25mhz ixel 1 pixel 2 .: pixel period : 20 nsec s dark aturated in the figure, shown from bottom to top: clock_x, sync_x and output. output level before the first pixel is the level of the last pixel on previous line. as soon as sync_x is high and one rising edge of clock_x occurs, the pixels are brought to the analog outputs. this is again the simulation result of a comparable sensor to show the principle. note the time difference between the clock edge and the moment the data is seen at the output. because it is dif ficult to predict this time difference in advance, have the adc sampling clock flexible to set an optimal ?add sampling? point. the time differences can easily vary between 5 ns and 15 ns and must be tested on the real devices. reduced rot timing the rot is the time between the selection of lines that you must wait to get the data stable at the column amplifiers. it is a loss in time, which should be reduced as much as possible. standard timing (200 ns) in this case, the control signals norowsel and pre_col are made active for about 20 ns from the moment the next line is selected. the time these pulses must be active is related to the biasing resistance pre_load. the lower this resistance, the shorter the pulse duration of norowsel and pre_col may be. after these pulses are given, wait for at least 180 ns before the first pixel is sampled. for this mode, sh_col must always be active (low). figure 19. standard timing for rot (only pre_col and no_row_sel control signals are required) in this case, the control signals norowsel and pre_col are made active for about 20 ns from the moment the next line is selected. the time these pulses must be active is related to the biasing resistance pre_load. the lower this resistance, the shorter the pulse duration of norowsel and pre_col may be. after these pulses are given, wait for at least 180 ns before the first pixel is sampled. for this mode sh_col must be made active (low) all the time.
NOIL1SM4000A http://onsemi.com 18 backup timing (rot = 100 to 200 ns) use a sample and hold function to reduce the rot. track the analog data using sh_col during the first 100 ns during the selection of a new set of lines. after 100 ns, the analog data is stored. the rot is reduced to 100 ns, but as the internal data is not stable yet, dynamic range is lost. this is because the complete analog levels are not reached after 100 ns. figure 20 shows this principle. sh_col is now a pulse of 100 ns to 200 ns starting at the same time as pre_col and norowsel. the duration of sh_col is equal to the rot. the shorter this time the shorter the rot; however, this also lowers the dynamic range. if voltage-averaging is required, the sensor must work in this mode with sh_col signal and a voltage-averaging signal must be generated after sh_col drops and before the readout starts (see figure 16 on page 15). figure 20. reduced standard rot with sh_col signal pre_col (short pulse), norowsel (short pulse) and sh_col (large pulse) precharging the buses this timing mode is similar to the mode without sample and hold, except that the prebus1 and prebus2 signals are activated. note that precharging of the buses can be combined with all the timing modes discussed earlier. the idea is to have a short pulse of about 5 ns to precharge the output buses to a known level. this mode makes the ghosting of bad columns impossible. in this mode, nsf_load must be made much larger (at least 1 m ). figure 21. x and y addressing with precharging of buses
NOIL1SM4000A http://onsemi.com 19 table 8. readout timing specifications with precharging of buses symbol name value a sync_y > 20 ns b sync_y-clock_y > 0 ns c clock_y-sync_y > 0 ns d norowsel > 50 ns e pre_col > 50 ns f sh_col 200 ns (or cst low, depending on timing mode) g voltage averaging > 20 ns h sync_x-clock_x > 0 ns i prebus pulse as short as possible serial peripheral interface the spi is required to upload different modes. table 9 shows the parameters and their bit position. table 9. spi parameters parameter bit # remarks y-direction 0 1: from bottom to top y-address 1 to 10 bit 1 is lsb x-voltage averaging enable 11 1: enabled x-subsampling 12 1: subsampling x-direction 13 0: from left to right x-address 14 to 23 bit 14 is lsb number of output amplifiers 24 0: 1 output dac 25 to 31 bit 25 is lsb when all zeros are loaded into the spi, the sensor starts at pixel 0,0. the scanning is from left to right and from top to bottom. there is no sub sampling or voltage averaging and only one output is used. the dac has the lowest level at its output. when using sub sampling, only even x-addresses should be applied. figure 22. spi block diagram and timing d q c d q c spi_in to sensor clock_spi load_addr 32 outputs to sensor clock_spi spi_in e un ity c ell ntire uploadable block load_addr b0 b1 load_addr clock_spi spi_in command applied to sensor bit 0 bit 31 b2 b31
NOIL1SM4000A http://onsemi.com 20 pin list table 10 lists the pins and their functionalities. table 10. pin list (notes 1, 2 and 3) pad pin pin name pin type description 1 e1 sync_x input digital input. synchronises the x-address register. 2 f1 eos_x testpin indicates when the end of the line is reached. 3 d2 vdd supply power supply digital modules. 4 g2 clock_x input digital input. determines the pixel rate. 5 g1 eos_spi testpin checks if the data is transferred correctly through the spi. 6 f2 spi_data input digital input. data for the spi. 7 h1 spi_load input digital input. loads data into the spi. 8 h2 spi_clock input digital input. clock for the spi. 9 j2 gndo ground ground output stages 10 j1 out2 output analog output 2. 11 k1 out2dc output reference output 2. 12 m2 voo supply power supply output stages 13 l1 out1dc output reference output 1. 14 m1 out1 output analog output 1. 15 n2 gndo ground ground output stages. 16 p1 vaa supply power supply analog modules. 17 p2 gnda ground ground analog modules. 18 n1 va3 supply power supply column modules. 19 p3 vpix supply power supply pixel array. 20 q1 psf_load input analog reference input. biasing for column modules. connect with r = 1 m to vaa and decouple with c = 100 nf to gnda. 21 q2 nsf_load input analog reference input. biasing for column modules. connect with r = 5 k to vaa and decouple with c = 100 nf to gnda. 22 r1 muxbus_load input analog reference input. biasing for multiplex bus. connect with r = 25 k to vaa and decouple with c = 100 nf to gnda. 23 r2 uni_load_fast input analog reference input. biasing for column modules. connect with r = 10 k to vaa and decouple with c = 100 nf to gnda. 24 q3 pre_load input analog reference input. biasing for column modules. connect with r = 3 k to vaa and decouple with c = 100 nf to gnda. 25 q4 out_load input analog reference input. biasing for output stage. connect with r = 60 k to vaa and decouple with c = 100 nf to gnda. 26 n3 dec_x_load input analog reference input. biasing for x-addressing. connect with r = 2 m to vdd and decouple with c = 100 nf to gndd. 27 q5 uni_load input analog reference input. biasing for column modules. connect with r = 1 m to vaa and decouple with c = 100 nf to gnda. 28 q6 col_load input analog reference input. biasing for column modules. connect with r = 1 m to vaa and decouple with c = 100 nf to gnda. 29 q7 dec_y_load input analog reference input. biasing for y-addressing. connect with r = 2 m to vdd and decouple with c = 100 nf to gndd. 30 r3 vdd supply power supply digital modules. 31 m3 gndd ground ground digital modules. 32 l2 prebus1 input digital input. control signal to reduce readout time. 33 l3 prebus2 input digital input. control signal to reduce readout time.
NOIL1SM4000A http://onsemi.com 21 table 10. pin list (notes 1, 2 and 3) pad description pin type pin name pin 34 q8 sh_col input digital input. control signal of the column readout. 35 r4 pre_col input digital input. control signal of the column readout to reduce row-blanking time. 36 r5 norowsel input digital input. control signal of the column readout. 37 r6 clock_y input digital input. clock of the y-addressing. 38 r7 sync_y input digital input. synchronizes the y-address register. 39 k2 eos_y_r testpin indicates when the end of frame is reached when scanning in the ?right? direc- tion. 40 q9 temp_diode_p testpin anode of temperature diode. 41 q10 temp_diode_n testpin cathode of temperature diode. 42 r8 vpix supply power supply pixel array. 43 r9 vmem_l supply power supply vmem drivers. 44 r10 vmem_h supply power supply vmem drivers. 45 r11 vres supply power supply reset drivers. 46 q11 vres_ds supply power supply reset drivers. 47 r12 adc1_ref_low input analog reference input. low reference voltage of adc (see figure 7 on page 8 for exact resistor value.) 48 q12 adc1_linear_conv input digital input. 1= linear conversion; 0= gamma correction. 49 p15 adc1_bit_9 output digital output 1 <9> (msb). 50 q14 adc1_bit_8 output digital output 1 <8>. 51 q15 adc1_bit_7 output digital output 1 <7>. 52 r13 adc1_bit_6 output digital output 1 <6>. 53 r14 adc1_bit_5 output digital output 1 <5>. 54 r15 adc1_bit_4 output digital output 1 <4>. 55 p14 adc1_bit_3 output digital output 1 <3>. 56 q13 adc1_bit_2 output digital output 1 <2>. 57 r16 adc1_bit_1 output digital output 1 <1>. 58 q16 adc1_bit_0 output digital output 1 <0> (lsb). 59 p16 adc1_clock input adc clock input. 60 n14 adc1_gndd supply digital gnd of adc circuitry. 61 n15 adc1_vddd supply digital supply of adc circuitry (nominal 2.5 v). 62 l16 adc1_gnda supply analog gnd of adc circuitry. 63 l15 adc1_vdda supply analog supply of adc circuitry (nominal 2.5 v). 64 n16 adc1_bit_inv input digital input. 0 = no inversion of output bits; 1 = inversion of output bits. 65 m16 adc1_cmd_ss input analog reference input. biasing of second stage of adc. connect to v dda with r = 50 k and decouple with c = 100 nf to gnda. 66 l14 adc1_nalog_in input analog input of first adc. 67 m15 adc1_cmd_fs input analog reference input. biasing of first stage of adc. connect to v dda with r = 50 k and decouple with c = 100 nf to gnda. 68 m14 adc1_ref_high input analog reference input. high reference voltage of adc. see figure 7 on page 8 for exact resistor value. 69 k14 vres_ds supply power supply reset drivers. 70 j14 vres supply power supply reset drivers.
NOIL1SM4000A http://onsemi.com 22 table 10. pin list (notes 1, 2 and 3) pad description pin type pin name pin 71 j15 vpre_l supply power supply precharge drivers. must be able to sink current. can also be connected to ground. 72 j16 vdd supply power supply digital modules. 73 k15 vmem_h supply power supply vmem drivers. 74 k16 vmem_l supply power supply vmem drivers. 75 h15 adc2_ref_low input analog reference input. low reference voltage of adc. see figure 7 on page 8 for exact resistor value. 76 h16 adc2_linear_conv input digital input. 1= linear conversion; 0= gamma correction. 77 g16 adc2_bit_9 output digital output 2 <9> (msb). 78 f16 adc2_bit_8 output digital output 2 <8>. 79 e16 adc2_bit_7 output digital output 2 <7>. 80 g15 adc2_bit_6 output digital output 2 <6>. 81 g14 adc2_bit_5 output digital output 2 <5>. 82 f14 adc2_bit_4 output digital output 2 <4>. 83 e14 adc2_bit_3 output digital output 2 <3>. 84 d16 adc2_bit_2 output digital output 2 <2>. 85 e15 adc2_bit_1 output digital output 2 <1>. 86 f15 adc2_bit_0 output digital output 2 <0> (lsb). 87 d15 adc2_clock input adc clock input. 88 c15 adc2_gndd supply digital gnd of adc circuitry. 89 d14 adc2_vddd supply digital supply of adc circuitry (nominal 2.5 v). 90 b16 adc2_gnda supply analog gnd of adc circuitry. 91 b14 adc2_vdda supply analog supply of adc circuitry (nominal 2.5 v). 92 c16 adc2_bit_inv input digital input. 0 = no inversion of output bits; 1 = inversion of output bits. 93 a16 adc2_cmd_ss input biasing of second stage of adc. connect to v dda with r = 50 k and de- couple with c = 100 nf to gnda. 94 b15 adc2_analog_in input analog input second adc. 95 a15 adc2_adc2_cmd_fs input analog reference input. biasing of first stage of adc. connect to v dda with r = 50 k and decouple with c = 100 nf to gnda. 96 a14 adc2_ref_high input analog reference input. high reference voltage of adc. see figure 7 on page 8 for exact resistor value. 97 c14 vres_ds supply power supply reset drivers. 98 b13 vres supply power supply reset drivers. 99 a13 vmem_h supply power supply vmem drivers. 100 a9 vmem_l supply power supply vmem drivers. 101 a10 vpix supply power supply pixel array. 102 a11 reset input digital input. control of reset signal in the pixel. 103 a12 reset_ds input digital input. control of double slope reset in the pixel. 104 b7 mem_hl input digital input. control of vmem signal in pixel. 105 b8 precharge input digital input. control of vprecharge signal in pixel. 106 b9 sample input digital input. control of vsample signal in pixel. 107 b10 temp_diode_n testpin cathode of temperature diode. 108 b11 temp_diode_p testpin anode of temperature diode.
NOIL1SM4000A http://onsemi.com 23 table 10. pin list (notes 1, 2 and 3) pad description pin type pin name pin 109 b6 precharge_bias input analog reference input. biasing for pixel array. see table 3 on page 10 for exact resistor and capacitor value. 110 a8 photodiode testpin output photodiode. 111 a7 gndd ground ground digital modules. 112 b12 vdd supply power supply digital modules. 113 a6 eos_y_l testpin indicates when the end of frame is reached when scanning in the ?left? direc- tion. 114 a1 sync_y input digital input. synchronizes the y-address register. 115 a5 clock_y input digital input. clock of the y-addressing. 116 a2 norowsel input digital input. control signal of the column readout. 117 a3 volt. averaging input digital input. control signal of the voltage averaging in the column readout. 118 b5 pre_col input digital input. control signal of the column readout to reduce row-blanking time. 119 a4 sh_col input digital input. control signal of the column readout. 120 b1 prebus2 input digital input. control signal to reduce readout time. 121 b2 prebus1 input digital input. control signal to reduce readout time. 122 c1 dec_y_load input analog reference input. biasing for y-addressing. 123 d1 vpix supply power supply pixel array. 124 b4 va3 supply power supply column modules. 125 b3 gnda ground ground analog modules. 126 c2 vaa supply power supply analog modules. 127 e2 gndd ground ground digital modules. 1. all pins with the same name can be connected together. 2. all digital input are active high (unless mentioned otherwise). 3. all unused inputs should be tied to a non active level (for example, v dd or gnd).
NOIL1SM4000A http://onsemi.com 24 package drawing figure 23. lupa4000: 127 pin pga package drawing 001-07580 *c
NOIL1SM4000A http://onsemi.com 25 mechanical package specification mechanical specifications min typ max units package (pin 1 bottom left) cavity size 27000 x 29007 m die (with pin 1 to the bottom left, top view) die size 25610 x 27200 m die center, x offset to the center of package ( ? 50) 0 (+50) m die center, y offset to the center of package ( ? 50) 0 (+50) m die position, x tilt 1 1 deg die position, y tilt 1 1 deg die placement accuracy in package ( ? 50) (+50) m die rotation accuracy ? 1 1 deg optical center referenced from package center (x ? dir) ( ? 50) 15 (+50) m optical center referenced from package center (y ? dir) ( ? 50) ? 80 (+50) m glass lid glass window size ( ? 10%) 38.5 x 38.5 (+10%) mm glass window thickness 0.7 mm spectral range for window 400 1000 nm transmission of the glass window 92 % mechanical shock jesd22 ? b104c; condition g 2000 g vibration jesd22 ? b103b; condition 1 20 2000 hz mounting profile pb ? free wave soldering profile for pin grid array package recommended socket andon electronics (www.andonelectronics.com) 575 ? 16 ? 24 ? 127 ? 01s ? r29 ? l14
NOIL1SM4000A http://onsemi.com 26 glass lid the lupa4000 image sensor uses a glass lid without any coatings. figure 24 shows the transmission characteristics of the glass lid. as seen in figure 24, the sensor does not use infrared attenuating color filter glass. you must provide a filter in the optical path when using color devices. figure 24. transmission characteristics of glass lid handling precautions for proper handling and storage conditions, refer to the on semiconductor application note an52561. limited warranty on semiconductor?s image sensor business unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to seller?s published specifications and will be free from defects in material and workmanship for two (2) years following the date of shipment. if a defect were to manifest itself within 2 (two) years period from the sale date, on semiconductor will either replace the product or give credit for the product. return material authorization (rma) on semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean-room-approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. acceptance criteria specification the product acceptance criteria is available on request. this document contains the criteria to which the lupa4000 is tested before being shipped. ordering code definition n on semiconductor designator l1 = lupa image sensors opto m = mono e = color micro lens standard process functionality placeholder i oc commercial temp range d = glass w = windowless resolution: 4 megapixel l1 s m q = lcc w = wafer sales q 4000 a ? d
NOIL1SM4000A http://onsemi.com 27 acronyms acronym description adc analog-to-digital converter afe analog front end ansi american national standards institute bga ball grid array bl black pixel data cdm charged device model cds correlated double sampling cis cmos image sensor cmos complementary metal oxide semiconductor cmy cyan magenta yellow crc cyclic redundancy check dac digital-to-analog converter ddr double data rate dft design for test dnl differential nonlinearity dsnu dark signal nonuniformity eia electronic industries alliance esd electrostatic discharge fe frame end ff fill factor fot frame overhead time fpn fixed pattern noise fps frames per second fs frame start hbm human body model hmux horizontal multiplexer i2c inter-integrated circuit ieee institute of electrical and electronics engineers img regular pixel data acronym description inl integral nonlinearity ip intellectual property jtag joint test action group le line end ls line start lsb least significant bit lvds low-voltage differential signaling mbs mixed boundary scan msb most significant bit mtf modulation transfer function ndr nondestructive readout nir near infrared pga programmable gain amplifier pls parasitic light sensitivity prbs pseudo-random binary sequence prnu pixel random nonuniformity qe quantum efficiency rgb red green blue rms root mean square roi region of interest rot row overhead time s/h sample and hold snr signal-to-noise ratio spi serial peripheral interface tap test access port tbd to be determined tia telecommunications industry association tr training pattern upga micro pin grid array
NOIL1SM4000A http://onsemi.com 28 glossary blooming the leakage of charge from a saturated pixel into neighboring pixels. camera gain constant a constant that converts the number of electrons collected by a pixel into digital output (in dn). it can b e extracted from photon transfer curves. column noise variation of column mean signal strengths. the human eye is sensitive to line patterns so this noise is analyzed separately. conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. conversion gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. cds correlated double sampling. this is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. cfa color filter array. the materials deposited on top of pixels that selectively transmit color. color crosstalk the leakage of signal from one color channel into another when the imager is not saturated. the signal can leak through either optical means, in which a photon enters a pixel of the wrong color, or electrical means, in which a charge carrier generated within one pixel diffuses into a neighboring pixel. cra chief ray angle. oblique rays that pass through the center of a lens system aperture stop. color filter ar- ray, metal, and micro lens shifts are determined by the chief ray angle of the optical system. in general, optical systems with smaller cra are desired to minimize color artifacts dn digital number. the number of bits (8, 12, 14, ? ) should also be specified. dnl differential nonlinearity (for adcs) dsnu dark signal nonuniformity. this parameter characterizes the degree of nonuniformity in dark leakage cur- rents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. grating monochromator an instrument that produces a monochromatic beam of light. it typically consists of a broadband light source such as a tungsten lamp and a diffraction grating for selecting a particular wavelength. inl integral nonlinearity (for adcs) luminance light flux per unit area in photometric units (lux) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. irradiance light flux per unit area in radiometric units (w/m 2 ) lag the persistence of signal after pixel reset when the irradiance changes from high to low values. in a video stream, lag appears as ?ghost? images that persist for one or more frames. lux photometric unit of luminance (at 550 nm, 1 lux = 1 lumen/m 2 = 1/683 w/m 2 ) nir near infrared. nir is part of the infrared portion of the spectrum and has wavelengths in the approximate range 750 nm to 1400 nm. pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixel array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. photon transfer measurement in which a bare imager (no external lens) is irradiated with uniform light from dark to satura- tion levels. typically the source is collimated, monochromatic 550 nm light. chapter 2 of j. janesick?s book, scientific charge coupled devices, describes the technique in detail. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response nonuniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and converting them into electrons. it is photon wavelength and pixel color dependent. radiometric units units for light measurement based on physics. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. soft reset occurs when the reset transistor is operated below the threshold. hard reset occurs when the reset transistor is operated above threshold.
NOIL1SM4000A http://onsemi.com 29 reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. reverse saturation phenomenon in which the signal level decreases with increasing light intensity. it typically occurs at irradi - ance levels much higher than saturation, such as an image taken of the sun. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. row noise variation of row mean signal strengths. the human eye is sensitive to line patterns, so this noise is ana- lyzed separately. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodi- ode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wavelength. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux = 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. shot noise noise that arises from measurements of discretised quanta (electrons or photons). it follows a poisson distribution with the strength of the noise increasing as the square root of the signal. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels. tint integration time.
NOIL1SM4000A http://onsemi.com 30 appendix a: frequently asked questions q: how does the dual (multiple) slope extended dynamic range mode work? a: the green lines in figure 27 are the analog signal on the photodiode, which decrease as a result of exposure. the slope is determined by the amount of light at each pixel (the more light the steeper the slope). when the pixels reach the saturation level, the analog signal does not change despite further exposure. without any double slope, pulse pixels p3 and p4 reaches saturation before the sample moment of the analog values, no signal is acquired without double slope. when double slope is enabled a second reset pulse is given (blue line) at a certain time before the end of the integration time. this double slope reset pulse resets the analog signal of the pixels below this level to the reset level. after the reset the analog signal starts to decrease with the same slope as before the double slope reset pulse. if the double slope reset pulse is placed at the end of the inte gration time (90% for instance) the analog signal that reaches the saturation levels are not saturated anymore (this increases the optical dynamic range) at read out. note that pixel signals above the double slope reset level are not influenced by this double slope reset pulse (p1 and p2). figure 25. dual slope diagram p4 p3 p2 p1 reset level 1 reset level 2 saturation level total integration time reset pulse double slope reset pulse read out double slope reset time (usually 5- 10% of the total integration time) on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NOIL1SM4000A/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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